Self-Timed Iteration

Self-Timed Logic and the Design of Self-Timed Adders

Self-timed is self-checking

Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, and unde f ined states; the fourth state is used to signal ill...

Self-Timed FPGA Systems

Recently, there has been a renewal of interest in self-timed systems, due to their modularity, robustness, low-power consumption and average-case performance. Additionally, this paper argues that there are speciic beneets to adopting self-timed design for FPGAs. The mapping problems of placement, routing and partitioning are simpliied by not having a global clock constraint to meet, so more map...

Self-Timed Patterning

Timing and convergence constitute a serious and under-appreciated complication in developmental patterning. I demonstrate an algorithm design methodology that eliminates timing problems across a broad family of spatial patterning mechanisms, with discrete gradients and growing points as examples. Values are exchanged between modules using partially informative representations, which monotonical...

Self-Stabilization in Iteration Systems